This invention relates to the field of managing power and ground connections between a microchip-substrate and a second substrate and in particular to constructing power and ground planes within solder ball and solder land arrays.
The ever-increasing density improvements in silicon can be more fully exploited with corresponding wiring density improvements in chip carriers. Challenges to increased wire density have been met with ball grid array packaging designs. However, as the number of balls have increased such as with C4 flip-chip designs, so has the inductance. In addition, the need for a via for each ball has increased the difficulty of routing circuitry around the additional vias. In current ball grid array designs typically one half of the balls are associated with power or ground connections. As linewidths are reduced, inductance and routing problems will continue to become more severe.